The FTC2-HG-DCO module uses a 104-pin CFP2 MSA connector for all electrical interfaces with the host card, whereas the optical interfaces on the line side are provided through the optical receptacles on the CFP2. The module can be portioned into three functional parts: Tx path, Rx path and control & power block.
All control interface pins are routed to the MCU and oDSP. The MCU is also used for fast controls inside the module such as modulator bias adjustment, software image management, overall control coordination and status reporting.

Product Features
● Transmission reach beyond 1300 km/3000km over SMF for 200G/100G
● Hot-pluggable
● Support PM-16QAM (200G) and PM DQPSK/PM-QPSK (100G) modulation
● Supports SD-FEC
● Supports 100G/200G Flex-rate
● Supports OTU4/OTUC2/2 x 100GE/100GEsignaling
● Compliant with CEI-28G-MR specifications
● Compliant with OTL4.4/OTLC2/CAUI-4signaling
● Compliant with CFP2 MSA HardwareSpecification Rev. 1.0
● Compliant with OIF-CFP2-DCO-01.0
● Compliant with CFP MSA ManagementInterface Specification Version 2.6 (R06a)
● Power consumption: 26 W (200G)/21 W(100G)

Applications
● Edge DCI with extended Reach or with OLP protection
● IP Over Metro or Long Haul DWDM

Application
The module is designed to be used on the host board of system integrators to support transmission over DWDM links in Metro networks. As shown in Figure 2-1, it comprises high-data lanes, a single reference clock from hosts, a single 3.3 V power supply, an MDIO interface for module control and status report, and dedicated alarm and control pins. 

Environmental Specifications
The table below defines the environmental specifications of the FTC2-HG-DCO module.

Absolute Maximum Ratings
Operating or handling the module out of any specified absolute maximum rating is subject to permanent damage of the module.

Electrical Characteristics
A single +3.3 V power supply shall be provided by the host card through the  104-pin connector and internal DC/DC power converters are used to regulate the power for different components inside the module. The  +3.3 V  power supply  provided  by  the  host  shall  adhere to the  CFP2  MSA  Hardware Specification  version1.0  available  at  www.cfp-msa.org.  The  electrical  ground  is  isolated  from  the module chassis ground.
The power supply requirements are specified in Table 8-1 below. Those power classes for which the  maximum current per pin exceeds 1125 mA will require agreement from the electrical connector supplier.

NOTE
*1  Power consumption depends on the actual application condition. For 200G PM-16QAM typical  application, optical links should have enough OSNR margin with pre-BER better than 1.5e 2 and  power consumption is less than 26 W (200G with framer enabled)/21 W ( 100G with framer enabled).
*2 With framer disabled, the power consumption will be reduced to 25 W for 200G or 20 W for 100G. The FTC2-HG-DCO module supports alarm, control, and monitoring functions over an MDIO bus.This interface consists of eight pins listed in the table below.

MDIO pins

There are six control pins as listed in the following table to support real-time control via hardware pins.

Host-control pins

The PRG_CNTRL [2:1] signals have MSA defined default meanings that are listed in the CFP MSA implementation  agreement.  The  lower  two  bits  (hardware  interlock)  define  the  power  class  of  the module and must be kept static during initialization. When MOD_LOPWR is active, the maximum power consumption is < 2 W and the host can still communicate with the module via the MDIO interface.

The MOD_RSTN signal is run to a reset chip to generate a reset to the internal MCU and oDSP ASIC (RST_N). There are five alarm pins from the module back to the host.
The transmitter and receiver comply with the CEI-28G-MR electrical specification. The data lines are AC-coupled and terminated in the module according to the following figure from the CFP2 MSA. The termination also applies to the reference clock, TX monitor clock, and RX monitor clock.

Transmitter electrical output characteristics

Module-host alarm pins

All signals but MOD_ABS interface to the DSP ASIC. The PRG_ALRM [2:1] signals have MSA defined default meanings that are listed in the CFP2 implementation agreement.

Mechanical Specifications

Ordering Information

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